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Odd SPI master clock frequencies
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berndocklin
Joined: 20 Feb 2013, 18:55 Posts: 11
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Hi
I am having trouble with the SPI. RT3050 manual states that master clock is system clock/N^2. system clock is 320Mhz/3. Roughly makes 833kHz for N^2 == 128 (confirmed with logic analyzer). Seems that some slave devices (e.g. AVRs) have an issue with these frequencies as they usually expect e.g. 16Mhz/N^2 or other even clock frequencies.
Am I missing something? Bug in the driver?
In general the SPI spi-ramips, spi-dev or the RT3050 itself seems to behave in an odd way. The RT3050 only does half-duplex. spi-dev has a hard coded spi mode 0 but is clearly running mode 2 with cpol high on idle. I guess its a bug in one of the kernel drivers as manual states that cpol 0 is possible.
Any hints?
Thanks, Bernd
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04 Jun 2013, 20:01 |
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schueler-maroldt
Joined: 03 Sep 2012, 16:54 Posts: 6
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Hi Bernd, this is no Bug. you schold set the clock freq a little bit higher then you need. 320/3/6 will be 17.7 Mhz.
I have modified the SPI-Driver with full duplex and set it up for SD-Card with 25Mhz (26.66 Mhz) and speed up a little bit. cpol is fixed, you can only change it if you do it with bitbang SPI-driver, i have done bitbang SPI-driver too, but its very slow. see
I think the clock is no problem because the SPI has handshake and only the max speed is.
Is you compile your system, i can give you the Driver and my modified mach-carambola.c
_________________ regards Joerg
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14 Jun 2013, 14:45 |
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