I am having very intermittent stability issues using both Caraboot and pepe-2k.
Both u-boot versions assume a tRAS value of 40 ns
This was true when the Carambola2 module used the W9751G6JB25 DDR2 module.
However, I popped off the cap of a newer Carambola2 module and it now uses W9751G6KB25

According to line in include/configs/carambola2.h

#define CFG_DDR_CONFIG_VAL 0x7fbc8cd0

tRAS is still specified at 40 ns

Should the default safe value be at 45 ns???

See datasheets

Page 45 of
http://digichip.ru/datasheet/PDF/df799b ... G6JB25.pdf

Page 45 of
https://www.winbond.com/resource-files/ ... g6kbg1.pdf