Hi,

I'm trying to configure buitin UART (carambola 2) to work at 9600bps, 1 stop bit, even parity and 7 bits.
I can't achieve this.

Here is different combinations that I tried.

toptions.c_cflag &= ~PARENB;
toptions.c_cflag |= PARODD; // cause no parity

toptions.c_cflag &= ~PARENB;
toptions.c_cflag &= ~PARODD; // cause no parity

toptions.c_cflag |= PARENB;
toptions.c_cflag |= PARODD; // cause no parity

toptions.c_cflag |= PARENB;
toptions.c_cflag &= ~PARODD; // cause odd parity

With logic analyzer I read packets and see that I can set only ODD parity or no parity at all. There is no way to get EVEN parity.
The same result I get both with my own code and with stty tool.
Is there any issue in driver? According to pdf from here (viewtopic.php?f=5&t=396) this Atheros should support even parity mode.

Plus I can't set 7 bits per message. Is this supported by this UART?

Did you rebuild kernel to don't use serial console ?

Fixed.
https://github.com/8devices/openwrt-8de ... ed0c98ea7c